E
ADVANCE INFORMATION
June 1997
Order Number: 290608-001
n
Two 32-Byte Write Buffers
2.7
s per Byte Effective
Programming Time
n
Low Voltage Operation
2.7V or 3.3V V
CC
2.7V, 3.3V or 5V V
PP
n
100 ns Read Access Time (16 Mbit)
110 ns Read Access Time (32 Mbit)
n
High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n
System Performance Enhancements
STS Status Output
n
Industry-Standard Packaging
BGA* package, SSOP, and
TSOP (16 Mbit)
BGA* package and SSOP (32 Mbit)
n
Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n
100,000 Block Erase Cycles
n
Enhanced Data Protection Features
Absolute Protection with V
PP
= GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n
Configurable x8 or x16 I/O
n
Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n
ETOXTM V Nonvolatile Flash
Technology
Intel's Word-Wide FlashFileTM memory family provides high-density, low-cost, non-volatile, read/write storage
solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various
densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended
cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards.
Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure
code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection
with V
PP
at GND, selective block locking, and program/erase lockout during power transitions. These
alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel's 0.4
m ETOXTM V process technology. It comes in the
industry-standard 56-lead SSOP and
BGA packages. In addition, the 16-Mb device is available in the
industry-standard 56-lead TSOP package.
WORD-WIDE
FlashFileTM MEMORY FAMILY
28F160S3, 28F320S3
Includes Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel's website at http:\\www.intel.com
COPYRIGHT INTEL CORPORATION, 1997
CG-041493
*Third-party brands and names are the property of their respective owners.
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28F160S3, 28F320S3
3
ADVANCE INFORMATION
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description ...........................6
2.0 PRINCIPLES OF OPERATION .....................10
2.1 Data Protection ..........................................11
3.0 BUS OPERATION .........................................12
3.1 Read ..........................................................12
3.2 Output Disable ...........................................12
3.3 Standby......................................................12
3.4 Deep Power-Down .....................................12
3.5 Read Query Operation ...............................12
3.6 Read Identifier Codes Operation ................13
3.7 Write ..........................................................13
4.0 COMMAND DEFINITIONS ............................13
4.1 Read Array Command................................16
4.2 Read Query Mode Command.....................17
4.2.1 Query Structure Output .......................17
4.2.2 Query Structure Overview ...................19
4.2.3 Block Status Register ..........................20
4.2.4 CFI Query Identification String.............21
4.2.5 System Interface Information...............22
4.2.6 Device Geometry Definition .................23
4.2.7 Intel-Specific Extended Query Table ...24
4.3 Read Identifier Codes Command ...............25
4.4 Read Status Register Command................25
4.5 Clear Status Register Command................26
4.6 Block Erase Command ..............................26
4.7 Full Chip Erase Command .........................26
4.8 Write to Buffer Command...........................27
4.9 Byte/Word Write Command ........................27
4.10 STS Configuration Command...................28
4.11 Block Erase Suspend Command ..............28
4.12 Program Suspend Command ...................28
4.13 Set Block Lock-Bit Commands .................29
4.14 Clear Block Lock-Bits Command ..............29
5.0 DESIGN CONSIDERATIONS ........................39
5.1 Three-Line Output Control..........................39
5.2 STS and WSM Polling ................................39
5.3 Power Supply Decoupling ..........................39
5.4 V
PP
Trace on Printed Circuit Boards...........39
5.5 V
CC
, V
PP
, RP# Transitions..........................39
5.6 Power-Up/Down Protection ........................39
6.0 ELECTRICAL SPECIFICATIONS..................40
6.1 Absolute Maximum Ratings ........................40
6.2 Operating Conditions..................................40
6.2.1 Capacitance.........................................41
6.2.2 AC Input/Output Test Conditions .........41
6.2.3 DC Characteristics...............................42
6.2.4 AC Characteristics - Read-Only
Operations..........................................44
6.2.5 AC Characteristics - Write Operations .46
6.2.6 Reset Operations.................................48
6.2.7 Erase, Program, And Lock-Bit
Configuration Performance .................49
APPENDIX A: Device Nomenclature and
Ordering Information ..................................51
APPENDIX B: Additional Information ...............52
28F160S3, 28F320S3
E
4
ADVANCE INFORMATION
REVISION HISTORY
Number
Description
-001
Original version
E
28F160S3, 28F320S3
5
ADVANCE INFORMATION
1.0
INTRODUCTION
This datasheet contains 16- and 32-Mbit Word-
Wide FlashFile
TM
memory (28F160S3 and
28F320S3) specifications. Section 1 provides a
flash memory overview. Sections 2, 3, 4, and 5
describe the memory organization and functionality.
Section 6 covers electrical specifications for
extended temperature product offerings.
1.1
New Features
The Word-Wide FlashFile memory family maintains
basic compatibility with Intel's 28F016SA and
28F016SV. Key enhancements include:
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) Support
Low Voltage Technology
Enhanced Suspend Capabilities
They share a compatible Status Register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
Because of new feature and density options,
the devices have different manufacturer and
device identifier codes. This allows for software
optimization.
New software commands.
To take advantage of low voltage on the
28F160S3 and 28F320S3, allow V
PP
connection to V
CC
. The 28F160S3 and
28F320S3 do not support a 12V V
PP
option.
1.2
Product Overview
The Word-Wide FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 5 illustrates the memory
organization.
This family of products are optimized for fast factory
programming and low power designs. Specifically
designed for 3V systems, the 28F160S3 and
28F320S3 support read operations at 2.7V3.6V
Vcc with block erase and program operations at
2.7V3.6V and 5V V
PP
. High programming
performance is achieved through highly-optimized
write buffers. A 5V V
PP
option is available for even
faster factory programming. For a simple low power
design, V
CC
and V
PP
can be tied to 2.7V.
Additionally, the dedicated V
PP
pin gives complete
data protection when V
PP
V
PPLK
.
Internal V
PP
detection circuitry automatically
configures the device for optimized write
operations.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of devices. This allows device-independent,
JEDEC ID-independent, and forward- and
backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement).
Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device's
64-Kbyte blocks typically within t
WHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times. Block erase
suspend mode allows system software to suspend
block erase to read or write data from any other
block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the
system to read data or execute code from any other
flash memory array location.
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